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ispLSI 2032E
In-System Programmable SuperFASTTM High Density PLD Features
* SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC -- 1000 PLD Gates -- 32 I/O Pins, Two Dedicated Inputs -- 32 Registers -- High Speed Global Interconnect -- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic -- 100% Functionally and JEDEC Upward Compatible with ispLSI 2032 Devices * HIGH PERFORMANCE E CMOS TECHNOLOGY -- fmax = 225 MHz Maximum Operating Frequency -- tpd = 3.5 ns Propagation Delay -- TTL Compatible Inputs and Outputs -- 5V Programmable Logic Core -- ispJTAGTM In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port -- User-Selectable 3.3V or 5V I/O (48-Pin Package Only) Supports Mixed Voltage Systems -- PCI Compatible Outputs (48-Pin Package Only) -- Open-Drain Output Option -- Electrically Erasable and Reprogrammable -- Non-Volatile -- Unused Product Term Shutdown Saves Power * ispLSI OFFERS THE FOLLOWING ADDED FEATURES -- Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality -- Reprogram Soldered Devices for Faster Prototyping * OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS -- Complete Programmable Device Can Combine Glue Logic and Structured Designs -- Enhanced Pin Locking Capability -- Three Dedicated Clock Input Pins -- Synchronous and Asynchronous Clocks -- Programmable Output Slew Rate Control to Minimize Switching Noise -- Flexible Pin Placement -- Optimized Global Routing Pool Provides Global Interconnectivity
2 (R)
(R)
Functional Block Diagram
A0
Output Routing Pool (ORP)
Input Bus
A2
GLB
Logic Array
DQ
DQ
A5
DQ
A3
A4
0139Bisp/2000
Description
The ispLSI 2032E is a High Density Programmable Logic Device. The device contains 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032E features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 2032E offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2032E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. A7 (see Figure 1). There are a total of eight GLBs in the ispLSI 2032E device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. The device also has 32 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually
Copyright (c) 2003 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
November 2003
2032e_05
1
Input Bus
A1
DQ
A6
Output Routing Pool (ORP)
Global Routing Pool (GRP)
A7
Specifications ispLSI 2032E
Functional Block Diagram
Figure 1. ispLSI 2032E Functional Block Diagram
GOE 0
Output Routing Pool (ORP)
Output Routing Pool (ORP)
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 TDI/IN 0 TDO/IN 1
A0
A7
I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 I/O 24 I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 18 I/O 17 I/O 16
A1
Input Bus
A2
A5
A3
A4
TMS BSCAN Y0 Y1* TCK/Y2
Notes: *Y1 and RESET are multiplexed on the same pin
CLK 0 CLK 1 CLK 2
Input Bus
Global Routing Pool (GRP)
A6
0139/2032E
programmed to be a combinatorial input, output or bidirectional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. By connecting the VCCIO pins to a common 5V or 3.3V power supply, I/O output levels can be matched to 5V or 3.3V compatible voltages. When connected to a 5V supply, the I/O pins provide PCI-compatible output drive (48-pin device only). Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the ORP. Each ispLSI 2032E device contains one Megablock. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew.
Clocks in the ispLSI 2032E device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the outputs of the ispLSI 2032E are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the Lattice software tools.
2
Specifications ispLSI 2032E
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL PARAMETER Supply Voltage: Logic Core, Input Buffers Supply Voltage: Output Drivers Input Low Voltage Input High Voltage 5V 3.3V TA = 0C to +70C MIN. 4.75 4.75 3.0 0 2.0 MAX. 5.25 5.25 3.6 0.8 Vcc+1 UNITS V V V V V
Table 2-0005/2032E
VCC VCCIO1 VIL VIH
1. 3.3V I/O operation not available for 44-pin packages.
Capacitance (TA=25C, f=1.0 MHz)
SYMBOL PARAMETER Dedicated Input Capacitance I/O Capacitance Clock Capacitance TYP 6 7 10 UNITS pf pf pf TEST CONDITIONS VCC = 5.0V, VIN = 2.0V VCC = 5.0V, VI/O = 2.0V VCC = 5.0V, VY = 2.0V
Table 2-0006/2032E
C1 C2 C3
Erase/Reprogram Specification
PARAMETER Erase/Reprogram Cycles MINIMUM 10,000 MAXIMUM - UNITS Cycles
Table 2-0008/2032E
3
Specifications ispLSI 2032E
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V 1.5 ns 1.5V 1.5V See Figure 2
Table 2-0003/2032E
Figure 2. Test Load
+ 5V R1 Device Output R2 CL* Test Point
Output Load Conditions (see Figure 2)
TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 470 470 470 R2 390 390 390 390 390 CL 35pF 35pF 35pF 5pF 5pF
Table 2 - 0004A
*CL includes Test Fixture and Probe Capacitance.
0213A
C
DC Electrical Characteristics
Over Recommended Operating Conditions1
SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current I/O Active Pull-Up Current, non-PCI I/O Active Pull-Up Current, PCI
5
CONDITION IOL = 8 mA IOH = -4 mA 0V VIN VIL (Max.) (VCCIO - 0.2)V VIN VCCIO VCCIO VIN 5.25V 0V VIN 2.0V 0V VIN 2.0V VCCIO = 5.0V or 3.3V, VOUT = 0.5V VIL = 0.0V, VIH = 3.0V fTOGGLE = 1 MHz -225/-200 Others
MIN. - 2.4 - - - -10 -10 - - - -
TYP.3 - - - - - - - - - 85 65
MAX. UNITS 0.4 - -10 10 10 -150 -250 -200 -240 - - V V A A A A A mA mA mA mA
VOL VOH IIL IIH IIL-PU IOS1 ICC2,4,6
1. 2. 3. 4. 5. 6.
Output Short Circuit Current, non-PCI VCCIO = 5V, VOUT = 0.5V Output Short Circuit Current, PCI5 Operating Power Supply Current
One output at a time for a maximum duration of one second (VOUT = 0.5V). Characterized, but not 100% tested. Meaured using two 16-bit counters. Typical values are at VCC = 5V and TA = 25C. Unused inputs held at 0.0V. Available in 48-pin package only. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC.
Table 2-0007/2032E
4
Specifications ispLSI 2032E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST 2 4# COND. A A A - - - A - - - - A - B C B C - - DESCRIPTION1 -225 - - 225
1 tsu2 + tco1
-200 - - 200 167 250 2.5 - 3.5 5.5 - - - - -
-180 5.0 7.5 - - - - 4.0 - - 4.5 - 6.5 - 10.0 10.0 5.0 5.0 - -
MIN. MAX. MIN. MAX. MIN. MAX. 3.5 5.5 - - - - 2.5 - - 3.5 - 5.0 - 7.0 7.0 3.5 3.5 - -
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl
1. 2. 3. 4.
1 Data Prop. Delay, 4PT Bypass, ORP Bypass 2 Data Prop. Delay 3 Clk Frequency with Int. Feedback3 4 Clk Frequency with Ext. Feedback ( 5 Clk Frequency, Max. Toggle 6 GLB Reg. Setup Time before Clk, 4 PT Bypass 7 GLB Reg. Clk to Output Delay, ORP Bypass 8 GLB Reg. Hold Time after Clk, 4 PT Bypass 9 GLB Reg. Setup Time before Clk 10 GLB Reg. Clk to Output Delay 11 GLB Reg. Hold Time after Clk 12 Ext. Reset Pin to Output Delay, ORP Bypass 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 Ext. Synch. Clk Pulse Duration, High 19 Ext. Synch. Clk Pulse Duration, Low
180 125 200 3.0 - 0.0 4.0 - 0.0 - 4.0 - - - - 2.5 2.5
250 2.5 - 0.0 3.5 - 0.0 - 3.5 - - - - 2.0 2.0
USE 2032E-22 5 FOR NEW DESIGNS
- 2.5 - - - - 0.0 - 3.5 3.5 5.0 7.0 7.0 3.5 3.5 - - 0.0 - 3.5 - - - - 2.0 2.0
)
167
Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section.
Table 2-0030A/2032E
5
Specifications ispLSI 2032E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST 2 4# COND. A A A - - - A - - - - A - B C B C - - DESCRIPTION1 -135 - - 137
1 tsu2 + tco1
-110 - - 111 77.0 125 5.5 - 0.0 7.5 - 0.0 - 6.5 - - - - 4.0 4.0 10.0 13.0 - - - - 5.5 - - 6.5 - 12.5 - 14.5 14.5 7.0 7.0 - -
MIN. MAX. MIN. MAX. 7.5 10.0 - - - - 4.5 - - 5.5 - 9.0 - 12.0 12.0 6.0 6.0 - -
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl
1. 2. 3. 4.
1 Data Propagation Delay, 4PT Bypass, ORP Bypass 2 Data Propagation Delay 3 Clock Frequency with Internal Feedback3 4 Clock Frequency with External Feedback ( 5 Clock Frequency, Max. Toggle 6 GLB Register Setup Time before Clock, 4 PT Bypass 7 GLB Register Clock to Output Delay, ORP Bypass 8 GLB Register Hold Time after Clock, 4 PT Bypass 9 GLB Register Setup Time before Clock 10 GLB Register Clock to Output Delay 11 GLB Register Hold Time after Clock 12 External Reset Pin to Output Delay, ORP Bypass 13 External Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 External Synchronous Clock Pulse Duration, High 19 External Synchronous Clock Pulse Duration, Low
)
100 167 4.0 - 0.0 5.5 - 0.0 - 5.0 - - - - 3.0 3.0
Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section.
Table 2-0030B/2032E
6
Specifications ispLSI 2032E
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER Inputs #
2
DESCRIPTION
-225
-200
-180
MIN. MAX. MIN. MAX. MIN. MAX. - - - - - - - - - 0.8 1.7 - - - - 0.3 - - - - - - - 0.8 1.0 - 0.6 1.3 0.7 1.2 1.2 2.2 2.2 2.2 0.0 - - 0.7 1.3 2.5 4.2 2.8 1.0 0.0 1.0 1.5 1.5 1.5 2.0 0.8 1.0 2.7 - - - - - - - - - 0.4 1.3 0.7 - - - - - - - - - 0.3 2.7 - - - - 1.5 - - - - - - - 1.4 1.6 - 0.6 1.3 0.7 1.8 2.8 3.8 3.8 3.8 0.0 - - 0.7 1.1 2.9 5.9 3.7 1.1 0.6 1.3 1.5 2.8 2.8 2.2 1.4 1.6 3.5
UNITS
tio tdin
GRP
20 Input Buffer Delay 21 Dedicated Input Delay 22 GRP Delay 23 4 Product Term Bypass Path Delay (Combinatorial) 24 4 Product Term Bypass Path Delay (Registered) 25 1 Product Term/XOR Path Delay 26 20 Product Term/XOR Path Delay 27 XOR Adjacent Path Delay
3
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tgrp
GLB
ORP
torp torpbp
Outputs
36 ORP Delay 37 ORP Bypass Delay 38 Output Buffer Delay 39 Output Slew Limited Delay Adder 40 I/O Cell OE to Output Enabled 41 I/O Cell OE to Output Disabled 42 Global Output Enable 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
tob tsl toen todis tgoe
Clocks
tgy0 tgy1/2
Global Reset
1.2 1.4 -
tgr
45 Global Reset to GLB
USE 2032E-22
- - - - - - -
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
28 GLB Register Bypass Delay 29 GLB Register Setup Time before Clock 30 GLB Register Hold Time after Clock 31 GLB Register Clock to Output Delay 32 GLB Register Reset to Output Delay 33 GLB Product Term Reset to Register Delay 34 GLB Product Term Output Enable to I/O Cell Delay 35 GLB Product Term Clock Delay
0.8 1.7 - - - -
0.7
5 FOR NEW DE
- -
SIGNS
1.8 1.8 2.8 2.8 2.8 0.0 0.7 2.9 2.5 4.4 3.2 1.0 0.0 0.6 1.5 1.5 1.5 2.0 1.2 1.4 2.7
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/2032E
7
Specifications ispLSI 2032E
Internal Timing Parameters1
PARAMETER Inputs #
2
DESCRIPTION
-135
-110
MIN. MAX. MIN. MAX. - - - - - - - - - 0.3 3.0 - - - - 2.9 - - - - - - - 2.3 2.3 - 1.1 2.4 1.3 3.6 3.6 5.0 5.1 5.6 0.0 - - 0.7 1.1 4.4 6.4 5.2 1.3 0.3 1.2 10.0 3.2 3.2 2.8 2.3 2.3 6.4 - - - - - - - - - 0.5 4.0 - - - - 4.0 - - - - - - - 3.2 3.2 - 1.7 3.4 1.7 4.9 4.8 6.2 6.8 7.5 0.1 - - 0.6 1.8 5.9 7.1 7.0 1.5 0.5 1.2 10.0 4.0 4.0 3.0 3.2 3.2 9.0
UNITS
tio tdin
GRP
20 Input Buffer Delay 21 Dedicated Input Delay 22 GRP Delay 23 4 Product Term Bypass Path Delay (Combinatorial) 24 4 Product Term Bypass Path Delay (Registered) 25 1 Product Term/XOR Path Delay 26 20 Product Term/XOR Path Delay 27 XOR Adjacent Path Delay
3
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tgrp
GLB
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
ORP
28 GLB Register Bypass Delay 29 GLB Register Setup Time before Clock 30 GLB Register Hold Time after Clock 31 GLB Register Clock to Output Delay 32 GLB Register Reset to Output Delay 33 GLB Product Term Reset to Register Delay 34 GLB Product Term Output Enable to I/O Cell Delay 35 GLB Product Term Clock Delay 36 ORP Delay 37 ORP Bypass Delay 38 Output Buffer Delay 39 Output Slew Limited Delay Adder 40 I/O Cell OE to Output Enabled 41 I/O Cell OE to Output Disabled 42 Global Output Enable 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
torp torpbp
Outputs
tob tsl toen todis tgoe
Clocks
tgy0 tgy1/2
Global Reset
45 Global Reset to GLB 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
tgr
Table 2-0036B/2032E
8
Specifications ispLSI 2032E
ispLSI 2032E Timing Model
I/O Cell GRP Feedback Ded. In Comb 4 PT Bypass #23 GRP #22 Reg 4 PT Bypass #24 20 PT XOR Delays #25, 26, 27 Reset #45 D RST #29, 30, 31, 32 GLB Reg Bypass #28 GLB Reg Delay Q ORP Bypass #37 ORP Delay #36
#38, #39
GLB
ORP
I/O Cell
#21 I/O Delay #20
I/O Pin (Input)
I/O Pin (Output)
Control RE PTs OE #33, 34, CK 35 Y0,1,2 GOE 0 #43, 44 #42
#40, 41
0491/2032E
Derivations of tsu, th and tco from the Product Term Clock tsu
= = = 2.7 = = = = 2.3 = = = = 6.8 = Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.6 + 0.7 + 2.2) + (0.8) - (0.6 + 0.7 + 0.3) Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.6 + 0.7 + 2.8) + (1.7) - (0.6 + 0.7 + 2.2) Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.6 + 0.7 + 2.8) + (0.7) + (1.0 + 1.0)
th
tco
Note: Calculations are based upon timing specifications for the ispLSI 2032E-225L
Table 2-0042/2032E
9
Specifications ispLSI 2032E
Power Consumption
Power consumption in the ispLSI 2032E device depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. Figure 3. Typical Device Power Consumption vs fmax
150 140 130 120 110 ispLSI 2032E-180 and Slower ispLSI 2032E-225 and -200
Figure 3 shows the relationship between power and operating speed.
ICC (mA)
100 90 80 70 60 50 40 1 20 40 60 80
100 120 140 160 180 200 220 240
fmax (MHz)
Notes: Configuration of two 16-bit counters Typical current at 5V, 25C
ICC can be estimated for the ispLSI 2032E using the following equation: For 2032E-225 and -200: ICC = 4.5 + (# of PTs * 1.3) + (# of nets * Max freq * 0.0035) For 2032E-180 and Slower: ICC = 4.5 + (# of PTs * 1.02) + (# of nets * Max freq * 0.0035) Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0127A/2032E
10
Specifications ispLSI 2032E
Pin Description
NAME
I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 GOE 0 Y0 RESET/Y1
44-PIN PLCC PIN NUMBERS
15, 19, 25, 29, 37, 41, 3, 7, 2 11 35 16, 20, 26, 30, 38, 42, 4, 8, 17, 21, 27, 31, 39, 43, 5, 9, 18, 22, 28, 32, 40, 44, 6, 10
44-PIN TQFP PIN NUMBERS
9, 13, 19, 23, 31 35, 41, 1, 40 5 29 10, 14, 20, 24, 32, 36, 42, 2, 11, 15, 21, 25, 33, 37, 43, 3, 12, 16, 22, 26, 34, 38, 44, 4
48-PIN TQFP PIN NUMBERS
9, 14, 20, 25, 33, 38, 44, 1, 43 5 31 10, 15, 21, 26, 34, 39, 45, 2, 11, 16, 22, 27, 35, 40, 46, 3, 13, 17, 23, 28, 37, 41, 47, 4
DESCRIPTION
Input/Output Pins -- These are the general purpose I/O pins used by the logic array.
Global Output Enable input pin. Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. This pin performs two functions: - Dedicated clock input. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. - Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Input -- Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. Input -- This pin performs two functions. When BSCAN is logic low, it functions as an input pin to load programming data into the device. TDI/IN0 also is used as one of the two control pins for the ISP state machine. When BSCAN is high, it functions as a dedicated input pin. Input -- When in ISP mode, controls operation of ISP state machine. Output/Input -- This pin performs two functions. When BSCAN is logic low, it functions as an output pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. Input -- This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Serial Shift Register. When BSCAN is high, it functions as a dedicated clock input. This clock input is brought into the Clock Distribution Network and can be routed to any GLB and/or I/O cell on the device. Ground (GND) VCC Supply voltage for output drivers, 5V or 3.3V. All VCCIO pins must be connected to the same voltage level.
Table 2-0002/2032E
BSCAN
13
7
7
TDI/IN 01
14
8
8
TMS/NC2 TDO/IN 11
36 24
30 18
32 19
TCK/Y21
33
27
29
GND VCC VCCIO
1,
23
17, 39 6, 28
12, 18, 36, 42 6, 30
12, 34
24, 48
1. Pins have dual function capability. 2. NC pins are not to be connected to any active signals, VCC or GND.
11
Specifications ispLSI 2032E
Pin Configuration
ispLSI 2032E 44-Pin PLCC Pinout Diagram
GOE 0 I/O 27 I/O 26 I/O 25 I/O 24 GND I/O 23 I/O 22 I/O 21 I/O 20 I/O 19
6 5 4 3 2 1 44 43 42 41 40 I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC BSCAN
1TDI/IN
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
GND 1TDO/IN 1 I/O 8 I/O 9 I/O 10 I/O 11 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
39 38 37 36 35 34 33 32 31 30 29
I/O 18 I/O 17 I/O 16 TMS/NC2 RESET/Y11 VCC TCK/Y21 I/O 15 I/O 14 I/O 13 I/O 12
ispLSI 2032E
Top View
0
I/O 0 I/O 1 I/O 2
44PLCC/2032E
1. Pins have dual function capability. 2. NC pins are not to be connected to any active signals, VCC or GND.
ispLSI 2032E 44-Pin TQFP Pinout Diagram
GOE 0 I/O 27 I/O 26 I/O 25 I/O 24 GND I/O 23 I/O 22 I/O 21 I/O 20 I/O 19
44 43 42 41 40 39 38 37 36 35 34 I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC BSCAN
1TDI/IN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
GND 1TDO/IN 1 I/O 8 I/O 9 I/O 10 I/O 11 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
33 32 31 30
I/O 18 I/O 17 I/O 16 TMS/NC2 RESET/Y11 VCC TCK/Y21 I/O 15 I/O 14 I/O 13 I/O 12
ispLSI 2032E
Top View
29 28 27 26 25 24 23
0
I/O 0 I/O 1 I/O 2
44TQFP/2032E
1. Pins have dual function capability. 2. NC pins are not to be connected to any active signals, VCC or GND.
12
Specifications ispLSI 2032E
Pin Configuration
ispLSI 2032E 48-Pin TQFP Pinout Diagram
VCCIO GOE 0 I/O 27 I/O 26 I/O 25 I/O 24 GND I/O 23 I/O 22 I/O 21 I/O 20 I/O 19
48 47 46 45 44 43 42 41 40 39 38 37 I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC BSCAN
1TDI/IN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1TDO/IN
36 35 34 33
GND I/O 18 I/O 17 I/O 16 TMS/NC2 RESET/Y11 VCC TCK/Y21 I/O 15 I/O 14 I/O 13 I/O 12
ispLSI 2032E
Top View
32 31 30 29 28 27 26 25
0
I/O 0 I/O 1 I/O 2 GND
I/O 9 I/O 10 I/O 11 VCCIO
I/O 3
I/O 4 I/O 5
I/O 6
I/O 7
GND
I/O 8
1
48TQFP/2032E
1. Pins have dual function capability. 2. NC pins are not to be connected to any active signals, VCC or GND.
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Specifications ispLSI 2032E
Part Number Description ispLSI 2032E - XXX X XXX X
Device Family Device Number Speed 225 = 225 MHz fmax 200 = 200 MHz fmax 180 = 180 MHz fmax 135 = 135 MHz fmax 110 = 110 MHz fmax Grade Blank = Commercial Package J44 = PLCC T44 = TQFP T48 = TQFP Power L = Low
0212/2032E
ispLSI 2032E Ordering Information
COMMERCIAL
FAMILY fmax (MHz) 225 225 225 200 180 180 ispLSI 180 135 135 135 110 110 110 tpd (ns) 3.5 3.5 3.5 3.5 5.0 5.0 5.0 7.5 7.5 7.5 10.0 10.0 10.0 ORDERING NUMBER ispLSI 2032E-225LJ44 ispLSI 2032E-225LT44 ispLSI 2032E-225LT48 ispLSI 2032E-200LT48* ispLSI 2032E-180LJ44 ispLSI 2032E-180LT44 ispLSI 2032E-180LT48 ispLSI 2032E-135LJ44 ispLSI 2032E-135LT44 ispLSI 2032E-135LT48 ispLSI 2032E-110LJ44 ispLSI 2032E-110LT44 ispLSI 2032E-110LT48 PACKAGE 44-Pin PLCC 44-Pin TQFP 48-Pin TQFP 48-Pin TQFP 44-Pin PLCC 44-Pin TQFP 48-Pin TQFP 44-Pin PLCC 44-Pin TQFP 48-Pin TQFP 44-Pin PLCC 44-Pin TQFP 48-Pin TQFP
Table 2-0041/2032E
*2032E-225 recommended for new designs.
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